In recently developed complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) devices, the values produced at the outputs of individual pixels within a CMOS APS sensor array have been subjected to various image processing techniques. One of these techniques, for example, is to digitize a stream of output values produced by an APS sensor array and then to direct the stream of output values into a digital memory device for storage. The stored values may then be accessed by a separate digital signal processor (DSP) and subjected to various known data transformations in order to improve image quality, or apply various special effects. More recently, efforts have been made to integrate digital signal processing circuits directly onto a common substrate along with a CMOS APS sensor array. According to one device architecture, analog data values produced by the APS sensor array are converted to digital values by analog-to-digital conversion circuits and provided directly to an on-chip DSP for immediate signal processing.
Such digital signal processing includes linear operations such as addition, subtraction, averaging, among other functions, as well as other linear combinations of arbitrary coefficient values. For example, in a CMOS camera light intensity signal values from the camera's pixel array are averaged to determine an average light intensity value. The array light intensity value then can be used to establish the exposure setting for the CMOS camera. Currently, the light intensity volume is determined in the DSP region.
FIG. 1 shows a conventional CMOS APS array and processing circuitry 100 including an image acquisition device 102 coupled to a digital signal processor system 103. The image acquisition device 102 includes a plurality of pixel cells 104, a plurality of row lines 106 and a plurality of column lines 108. Each pixel cell 104 includes a respective photosensitive device 112 such as a photodiode or phototransistor and a respective switching device 124 such as a field effect transistor. Each respective transistor 124 includes a gate coupled to a respective one of the plurality of row lines 106 and a drain coupled to a respective one on the plurality of column lines 108. The plurality of row lines 106 are coupled to, and under the control of, a row decoder circuit 114. Each column line 108 is coupled to an input 126, 128, 130 of a respective column buffer circuit 132, 134, 136.
In operation, during an integration period for generating an image signal voltage (Vsig) for a given pixel, an image is projected on the array of pixel cells 104 of the image acquisition device 102. Each pixel cell 104 generates an electrical charge proportional to incident light intensity at its respective location. The row decoder 114 then selects one row (e.g., row 120) of pixel cells 104 by placing a selection signal on the selected row line 106. Then column lines 108, controlled by column decoder 150, are activated one by one to read out the voltage generated by the pixel cell 104 so they can be stored in a sample and hold circuit (not shown) of a respective column buffer circuit 132, 134, 136.
FIG. 2 shows a portion of the FIG. 1 circuit in additional detail. In FIG. 2, a sample and hold circuit 206 is shown within column buffer 136; sample and hold circuit 206 is representative of other sample and hold circuits within other column buffer circuits, e.g., within column buffer 132, 134. The sample and hold circuit 206 includes crawbar switch 218 and capacitors 222, 226. FIG. 2 also shows gain stage circuit 155 which includes gain stage amplifier 164 and feedback capacitors 278.
Turning back to FIG. 1, each column buffer circuit 132, 134, 136 has a respective control input 140, 142, 144. The respective control inputs 140, 142, 144 are coupled to, and operate under the control of, a column decoder circuit 150. Column decoder 150 activates a respective column buffer 132, 134, 136, by simultaneously activating the crawbar switch 218 and selection switches 232, 240 within the column buffer circuit, in order to steer the signals stored in the selected column buffer to the gain stage 155, and thereafter into the analog-to-digital converter 162. Column decoder 150 is programmed such that only one of column buffer circuits 132, 134, 136 is activated for readout, (i.e., the activation of the respective crawbar switch 218 and selection switches 232, 240 within the column buffer circuit 132, 134, 136) at a time. This restriction on the column decoder 150 is also referred to as being “interlocked.”
As seen in FIG. 1, each column buffer circuit 132, 134, 136 also has a respective analog output 152, 154, 156. The analog outputs 152, 154, 156 are mutually coupled through an analog gain stage 155, which includes differential amplifier 164, to an analog input 160 of an analog-to-digital converter (ADC) 162. Analog outputs 152, 154, 156 each represent a pair of outputs from a respective column buffer 132, 134, 136. Each respective pair of outputs is then differentiated by differential amplifier 164. The output of differential amplifier 164 (Vdiff) is referred to as:Vdiff=Vin—p−Vin—n  (1)
In Eq. (1), Vin_p refers to a first signal voltage from a pixel and Vin_n refers to a second signal voltage from the same pixel. Typically, in a three transistor APS pixel, Vin_p corresponds to a reset signal voltage (e.g., Vrst) and Vin_n corresponds to an image signal voltage (e.g., Vsig).
Once Vdiff has been digitized by ADC 162, it is often desirable, and occasionally required, that a plurality of readings of Vdiff (e.g., received from a corresponding plurality of column buffer circuits) be combined with each other. For example, combining the Vdiff from a first and second pixel.
It is known to combine signals from different column buffer circuits in the digital domain of an imager by combining the (post ADC amplifier) Vdiff signals from the column buffer circuits. However, combining the signals from the column buffer circuits in the analog region of the imager could reduce the amount of noise introduced into the combined signal. Therefore, it is desirable to combine signals from different volume buffer circuits in the analog region of the imager to reduce the introduction of spurious noise into the outputted signal.